Reliability Modeling and Mitigation for Embedded Memories

CMOS technology scaling has faced over the past recent decades significant variability and reliability challenges both from the manufacturing and operational point of view. It is well recognised that Bias Temperature Instability (BTI) is one of the most (if not the most) aging mechanisms for CMOS technology. The impact of such mechanism has been heavily studied for memory cell array of SRAMS, but not enough for peripheral circuit and its overall impact on the memory functionality. This paper quantifies the impact of BTI on the write path and read path of an SRAM while considering different supply voltages, temperatures, workloads and technology nodes. The results show that the BTI impact is marginal for the write circuitry, irrespective of the workload and technology. In contrast, the impact is much higher (~3× more) for the read path, where the sense amplifier (SA) is the most sensitive part. Therefore, a mitigation scheme for the SA is proposed and evaluated. The results show that the SA offset voltage specification can be reduced significantly (~3.5×).