Energy-Efficiency Exploration of Memory Hierarchy using NVMs for HEVC Motion Estimation

2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)(2019)

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摘要
Efficient video coding techniques applied by modern video encoders - e.g. the High Efficiency Video Coding (HEVC) - enable the handling and sharing of digital videos content. The applied complex data-intensive algorithms, as the Motion Estimation (ME), pose severe constraints in terms of memory communication and energy consumption, especially for battery-powered devices. Thus, an evaluation using efficient memory hierarchies, exploring multiple cache configurations and the use of non-volatile memories (NVMs) as main memory, was performed. Our evaluation considered TZS algorithm, encoding FHD videos, under 32 different cache configurations, combined with three main memory technologies: DRAM, STTRAM, and ReRAM. The best cache configurations were selected in terms of lowest total energy consumption, moreover, different energy savings were achieved using non-volatile memories as main memory, varying from 33.4% to 57.6%, for STTRAM and ReRAM, respectively, with ReRAM presenting the best energy results and reducing the optimal cache size.
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关键词
ReRAM,STTRAM,video coding,cache memory,motion estimation
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