Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability Estimation
VLSI-SoC(2019)
摘要
The circuit reliability in nanometer technologies has become an important aspect of circuit design. Techniques to improve reliability usually increase project costs. To avoid overdesign, techniques to estimate circuit reliability are commonly used. These techniques usually explore probabilistic Matrices to compute the circuit reliability. The matrices used to represent logic functions are simplified do not taking into account the logic gate design. In this way, the main goal of this thesis is to propose a method capable of creating probabilistic matrices from logic gates layouts and then improve the accuracy of the reliability evaluation methods.
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关键词
logic gates layout,circuit reliability estimation,circuit design,probabilistic matrices,logic gate design,reliability evaluation methods,nanometer technologies,project costs,logic functions
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