Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability Estimation

The circuit reliability in nanometer technologies has become an important aspect of circuit design. Techniques to improve reliability usually increase project costs. To avoid overdesign, techniques to estimate circuit reliability are commonly used. These techniques usually explore probabilistic Matrices to compute the circuit reliability. The matrices used to represent logic functions are simplified do not taking into account the logic gate design. In this way, the main goal of this thesis is to propose a method capable of creating probabilistic matrices from logic gates layouts and then improve the accuracy of the reliability evaluation methods.