A Simplified Layout-Level method for Single Event Transient Faults Susceptibility on Logic Gates

The progressive downscaling of feature sizes increases the susceptibility to Single Event Effects in integrated circuits. As a manner to mitigate soft errors, solutions incur significant performance and area penalties, especially when a design with fault-tolerant structure is overprotected. Probabilistic methods such as Probabilistic Transfer Matrix and Signal Probability Reliability Multi-Pass are prone to multiple faults scenario to evaluate circuits reliability. However, it is necessary that the probabilistic matrices of the gates being accurate enough for this task. This paper proposes a method to evaluate gate failure rate considering faults in Layout-Level. This method can be used to enrich the probabilistic matrices creation taking into account the characteristics of the layout in order to evaluate gate reliability and the failure rate more precisely. Results show a reduction of 40% in the failure rate just choosing the best layout alternative for the same logic function.