A 10mW 16b 15MS/s Two-Step SAR ADC with 95dB DR Using Dual-Deadzone Ring-Amplifier

Low-noise ring amplifiers required for high-precision analog–digital converters (ADCs) greater than 16 b remain unexplored. This article demonstrates a two-step successive approximation (SAR) ADC achieving 91-dB signal-to-noise-and-distortion-ratio (SNDR) with 6-V differential input resulting in a low-frequency Schreier-figure-of-merit ( $\text {FOM}_{S,lf}$ ) of 179.8 dB at 15 MS/s. The state-of-the-art performance is enabled by the ring-amplifier design that enables low noise during amplification and robust control of the transient dynamics. The ADC also features an on-chip residue amplifier (RA) settling characterization using the backend SAR ADC. The ADC is fabricated in a 180-nm CMOS process and occupies an active area of 1.82 mm ² .