Challenges and opportunities of wireless network-on-chip for manycore architectures

Increasing core count heralds the arrival of massive shared-memory chip multiprocessors. For such a scenario, traditional on-chip networks have been proven to not scale well neither in terms of transmission latency nor in terms of energy consumption. The Wireless Network-on-Chip (WNoC) paradigm holds considerable promise for the implementation of fast and efficient on-chip networks in such massive multi-core chips. In this talk, we will first provide an overview of the multiple opportunities that WNoC opens up from the computer architecture perspective. The talk will then move on to enumerate the different challenges that WNoC architectures currently face in each of the multiple layers of the stack, which we will have to overcome before the first integrated prototype becomes a reality. Overall, this talk aims to make a case for NoC-WNoC hybrid architectures, and hopes to motivate researchers from multiple disciplines to work towards its mainstream adoption.