A Femto/Pico-Watt Feedforward Leakage Self-Suppression Logic Family in 180 nm to 28 nm Technologies

We present a novel logic family, titled feedforward leakage self-suppression logic (FLSL), for nanowatt and sub-nanowatt always-on circuits. It addresses the prohibitively long delay of existing ultra-low leakage logic families without requiring sleep or mode control signals to exercise the leakage-suppression mode. Implemented in 180-nm CMOS, the proposed logic family achieves femto-watt per-gate leakage and a fan-out-of-4 (FO4) delay of 10.2 mu s, a remarkable speed enhancement of 150X over the prior art in the same process in the same leakage level. We also investigate the impact of technology scaling by designing the FLSL logic family additionally in 65-nm and 28-nm processes. In a 28-nm process, the FLSL can achieve about 70 ns FO4 delay and 10 picowatts per-gate leakage. Finally, we prototype a finite impulse response filter core for physical sensing systems in a 180 nm. The filter can achieve the power consumption of 109 picowatts for sparse, i.e., predominantly constant or slowly changing, input signals at 1 kHz clock frequency.