Improved Current Collapse in Recessed AlGaN/GaN MOS-HEMTs by Interface and Structure Engineering

Enhancement-mode (E-mode) GaN MOS-HEMTs using recess process typically face the challenge of precise thickness control, surface roughness issue, and interface traps, all of which could lead to the degradation of the device performance and cause reliability issues. In this article, we use a combined process of atomic layer etching (ALE) technique and atomic layer deposited (ALD) HfSiO dielectric. ALE is repeated oxidation and dry etching process with minimal surface damage, leading to a precisely controlled low-damage recess channel area. The fabricated AlGaN/GaN MOS-HEMTs exhibit E-mode operation with a positive threshold voltage ( ${V}_{\text {th}}$ ) of +2.1 V with small ${V}_{\text {th}}$ dispersion for different devices, an ultrahigh drain current ON– OFF ratio over 10 ¹⁰ and a low ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) of $11.5~\Omega \cdot \text {mm}$ at gate-to-drain length ( ${L}_{\text {GD}}$ ) of $25~\mu \text{m}$ . Source field plate (SFP) structure is employed to reduce the charge trapping process and improve the reliability at high voltages. The current collapse of the E-mode device with SFP structure can be effectively suppressed due to the optimized redistribution of the peak electric field in the gate-to-drain access region, where a significantly improved dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of only 1.17 times increase from the static ${R}_{ \mathrm{\scriptscriptstyle ON}}$ after OFF-state ${V}_{\text {DS}}$ stress of 600 V. Moreover, the enhanced vertical electric field with decreased AlGaN barrier thickness and the positive shift in threshold voltage for the E-mode device can effectively suppress the current collapse, which outperforms the depletion-mode counterpart. The breakdown voltage reaches a considerable value of 1560 V at an OFF-state current density of ${1}~\mu \text{A}$ /mm.