Modeling Interface Charge Traps in Junctionless FETs, Including Temperature Effects

In this article, an analytical predictive model of interface charge traps in symmetric, long-channel double-gate, junctionless transistors (JLTs) is proposed based on a charge-based model. Interface charge traps arising from exposure to chemicals, high-energy ionizing radiation, or aging mechanism could degrade the charge–voltage characteristics. The model is predictive in a range of temperatures from 77 to 400 K. The validity of the approach is confirmed by extensive comparisons with numerical technology computer-aided design (TCAD) simulations in all regions of operation from deep depletion to accumulation and from linear to saturation.