A Highly Linear Neuromorphic Synaptic Device Based on Regulated Charge Trap/Detrap

In this letter, we present highly linear potentiation/depression behaviors of a neuromorphic synaptic device made of CMOS-compatible floating gate (FG) cells. The kinetics of the charge trap/detrap mechanism under various pulse shapes are analyzed to design a simple 2C-4T FG cell with a modulated column write driver for embedded incremental step pulse programming (ISPP) via analog feedback. Utilizing real-time ISPP, the linearity and symmetry of the weight update were significantly improved due to the content-aware programming strength. Moreover, the proposed circuit technique provides flexibility regarding the size of the program/erase steps in addition to the superior linearity. The proposed FG cells with peripheral circuits are fabricated using 180nm CMOS technology and exhibited a differential non-linearity (DNL) less than 0.946 least significant bit (LSB) with 100 weight states. The excellent linearity remains unchanged even when the directions of potentiation /depression are reversed throughout the entire range.