A Scalable and Reconfigurable in-Memory Architecture for Ternary Deep Spiking Neural Network with ReRAM Based Neurons

Neuromorphic computing using post-CMOS technologies is gaining increasing popularity due to its promising potential to resolve the power constraints in Von-Neumann machine and its similarity to the operation of the real human brain. In this work, we propose a scalable and reconfigurable architecture that exploits the ReRAM-based neurons for deep Spiking Neural Networks (SNNs). In prior publications, neurons were implemented using dedicated analog or digital circuits that are not area and energy efficient. In our work, for the first time, we address the scaling and power bottlenecks of neuromorphic architecture by utilizing a single one-transistor-one-ReRAM (1T1R) cell to emulate the neuron. We show that the ReRAM-based neurons can be integrated within the synaptic crossbar to build extremely dense Process Element (PE)–spiking neural network in memory array–with high throughput. We provide microarchitecture and circuit designs to enable the deep spiking neural network computing in memory with an insignificant area overhead. Simulation results on MNIST and CIFAR-10 datasets with spiking Resnet (SResnet) and spiking Squeezenet (SSqueez) show that compared to the baseline CPU only solution, our proposed architecture achieves energy saving between 1222 ×  and 1853 ×  and speed improvement between 791 ×  to 1120 ×.