Submodule Test Circuit For Mmc-Based Hvdc System With Reduced Current Distortion

Byuong-Jun Seo, Kwon-Sik Park,Kwang-Rae Jo, Jin-Yong Heo,Eui-Cheol Nho

2019 10TH INTERNATIONAL CONFERENCE ON POWER ELECTRONICS AND ECCE ASIA (ICPE 2019 - ECCE ASIA)(2019)

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摘要
This paper deals with a submodule test circuit for MMC-based HVDC system. A submodule input current contains not only AC but also DC components in the real operating HVDC system. The submodule test circuit can generate submodule input current which is similar to that in real HVDC system. In order to control the submodule input current, PR, PI, and feedforward controllers are combined. Among them, the feedforward controller is used to eliminate current distortion. Simulation results for 2 kV 600 A submodule show the usefulness of the proposed control method.
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关键词
HVDC, Submodule test, Modular multi-level converter
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