A 14-bit 250-MS/s charge-domain pipelined ADC with mix-signal foreground calibration

A mix-signal foreground calibration method for charge domain pipelined ADC is proposed. The calibration method can calibrate the common-mode and differential-mode charge errors caused by capacitor mismatches stage by stage based on a binary search. Common-mode and differential-mode charge errors caused by the capacitor mismatches in charge domain pipelined substage circuits can be compensated for by the proposed calibration method. Based on the proposed calibration method, a 14-bit 250-MS/s charge domain pipelined ADC is designed and realized in a 1P6M 0.18 μm CMOS process. Test results show that the 14-bit 250-MS/s ADC achieves a signal-to-noise ratio of 70.5 dBFS and a spurious free dynamic range of 88.7 dB, with 20.1 MHz input at 250-MS/s, while the ADC core consumes 235 mW of power and occupies an area of 3.2 mm 2 .