A Low Power Fully-Integrated 76-81 Ghz Adpll For Automotive Radar Applications With 150 Mhz/Us Fmcw Chirp Rate And-95dbc/Hz Phase Noise At 1 Mhz Offset In Fdsoi

In this paper, a fully integrated 76-81 GHz All Digital PLL for FMCW automotive radar applications is presented. It features a 20 GHz digital PLL followed by a 4x multiplier and buffer. The proposed ADPLL is implemented in a 22nm fully depleted SOI CMOS technology. It achieves up to 150 MHz/us FMCW chirp rate over a 4 GHz bandwidth and dissipates 85mW only.