A Highly Linear Multi-Level SC DAC in a Power-Efficient Gm-C Continuous-Time Delta-Sigma Modulator

A highly linear multi-level switched-capacitor (SC) digital-to-analog converter (DAC) is proposed for continuous-time delta-sigma modulators (CTDSMs). A Gm-C CTDSM with a passive frontend low-pass filter (LPF) is further proposed to mitigate the problems of increased settling requirements and worsened anti-aliasing capability (consequences of an SC DAC) so as to realize an extremely power-efficient CTDSM. A 100-kHz bandwidth $40\times $ oversampling 3rd-order CTDSM prototype employing the proposed DAC and modulator topology is fabricated in a low-leakage 65-nm CMOS technology. Experimental results show that the modulator achieves a spurious-free dynamic range (SFDR), dynamic range (DR) and signal-to-noise and distortion ratio (SNDR) of 86.6 dB, 85.1 dB and 78.8 dB, respectively. To the best of our knowledge, this is the first silicon-proven CTDSM with a more-than-3-level DAC that leads to an excellent SFDR while not requiring dynamic element matching, component calibration, precise reference voltages, or an operating frequency higher than the modulator’s sampling frequency ${{f}}_{{{s}}}$ . The prototype consumes 22.8 $\mu \text{W}$ from a 1.2-V supply, amounting to a Walden’s and Schreier’s figure of merit (FoM) of 16 fJ/conv.-step and 181.5 dB, respectively, which is the best among state-of-the-art CTDSMs. It further achieves high alias rejections of 52 dB and 58 dB at ${{f}}_{{{s}}}$ and $2{{f}}_{{{s}}}$ , respectively, and can tolerate a clock period jitter of 3 ns.