A 77dB-SFDR Multi-Phase-Sampling 16-Element Digital Beamformer with 64 4GS/s 100MHz-BW Continuous-Time Band-Pass ΔΣ ADCs

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)(2019)

引用 2|浏览9
暂无评分
摘要
This paper tackles the fundamental limitation of distortion in large-scale digital beamforming. SNR improves by 3dB for every doubling of array size; however, distortion is correlated and so is not improved by the array gain. This work introduces the concept of multiple ADCs per element, with each sampling at a different phase, to both reduce distortion of the ADCs and RF frontend. A further advantage is that multi-phase-sampling with continuous-time band-pass delta-sigma modulators (CTBPDSMs) reduces the ADC clock-jitter sensitivity. A prototype 16-element 1GHz-IF digital beamformer employs four multi-phase-sampling sub-ADCs per element. The prototype beamformer IC integrates 64 4GS/s sub-ADCs and digital processing to generate four simultaneous beams. Bit-stream digital beamform processing efficiently handles the aggregate 0.256TS/s from the entire ADC array. The measured beamformer SNDR and SFDR are 56dB and 77dB, respectively. Multiphase sampling improves measured HD3 by 9dB.
更多
查看译文
关键词
Digital beamforming,phased-array,receiver,linearity,delta-sigma modulator (ΔΣM)
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要