25 Gb/S Nrz And 50 Gb/S Pam-4 Transimpedance Amplifier With Active Feedback And Equalization In 90 Nm Cmos Technology

In this paper, a high-linearity transimpedance amplifier (TIA) was designed in 90 nm CMOS technology. The input stage of the TIA was a regulated cascade circuit for low input impedance. The active feedback structure was used to replace the feedback resistor and to reduce the chip size. An equalizer was also used in the TIA to compensate the high-frequency response. Within input current amplitude of 1.1 mA, the total harmonic distortion of the TIA can be below 5%. The bandwidth of the TIA was about 26 GHz and its input-referred current density was below 74 pA root Hz within the bandwidth. The TIA can be applied in 25 Gb/s non-return zero (NRZ) and 50 Gb/s (25 Gbaud) four-level pulse amplitude modulation (PAM-4) optical receivers. The power dissipation of the chip is 11.6 mW and the chip area is 0.151 mm(2).