Device-, Circuit- & Block-level evaluation of CFET in a 4 track library
2019 Symposium on VLSI Technology(2019)
摘要
The structure of the complementary FET (CFET) with NMOS stacked on top of PMOS, inherently yields standard cells and SRAM cells with 25% smaller layout area, 25% higher pin density and 2× higher routing flexibility than FinFET with same overall active footprint. Moreover, our work, based on advanced modelling, demonstrates that 4 track CFET can match and even outperform 5 track FinFET; without the need to lower S/D contact resistivity down to 5e-10Ω.cm
2
or to elevate the channel stress up to 2GPa. All gains in power-performance-area at circuit-level are maintained at block-level, making 4 track CFET a suitable candidate for N3 & N2 technologies.
更多查看译文
关键词
power-performance-area,block-level evaluation,complementary FET,NMOS,PMOS,standard cells,SRAM cells,active footprint,advanced modelling,circuit-level evaluation,pin density,routing flexibility,track library,track FinFET,track CFET,S/D contact resistivity,device-level evaluation,N2 technologies,N3 technologies,pressure 2.0 GPa
AI 理解论文
溯源树
样例
![](https://originalfileserver.aminer.cn/sys/aminer/pubs/mrt_preview.jpeg)
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要