Threshold Voltage Tuning Of 22 nm FD-SOI Devices Fabricated With Metal Gate Last Process

In this work, an advanced 22 nm fully depleted silicon-on-insulator (FD-SOI) process for very large scale integrated circuit (VLSI) is demonstrated. High-k first, metal gate last process is applied in this work, allowing wide tuning of threshold voltage. The fabricated N-type MOSFET (NFET) and P-type MOSFET (PFET) show very good short channel effect (SCE) control. Thanks to the hybrid region, back gate bias can to applied to FD-SOI devices and be used as a tuning knob of threshold voltage, sensitivity of threshold voltage to back gate bias is found to be -72 mV/V and -66 mV/V for N-type MOSFET (NFET) and P-type MOSFET (PFET). Well doping is also used as a tuning knob for threshold voltage tuning. By reversely dope the well, a reduction of |V _thlin | by 60 mV and 80 mV for NFET and PFET have been observed.