Unaligned Burst-Aware Memory Subsystem.

In this paper, we present a memory subsystem for a burst that is unaligned to a block of synchronous dynamic random access memory (SDRAM) columns. In the case that a processor demands such an unaligned burst, a memory subsystem is required to rearrange SDRAM transfers in the order demanded by the processor. Our memory subsystem modifies a memory address given by a processor, then accesses SDRAMs w...