A Background Timing Skew Calibration Technique In Time-Interleaved Adcs
2019 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC)(2019)
Abstract
This paper presents a background timing skew calibration technique for time-interleaved analog-to-digital converters(ADCs). The timing skew between two adjacent sub-ADCs is detected in the digital domain through slope-based and statistics-based technique. Based on the detection error, the digitally controlled delay line(DCDL) is driven to minimum the timing skew. Using the proposed calibration algorithm in a 14-bit SOOMSIs TI ADC model, the MATLAB simulation result shows a convergence time of 346ms under Nyquist frequency input with 1%.Ts initial timing mismatch, and the proposed method can effectively reduce hardware consumption in circuit implementation.
MoreTranslated text
Key words
timing skew, background calibration, time interleaved ADCs, MATLAB simulation
AI Read Science
Must-Reading Tree
Example
![](https://originalfileserver.aminer.cn/sys/aminer/pubs/mrt_preview.jpeg)
Generate MRT to find the research sequence of this paper
Chat Paper
Summary is being generated by the instructions you defined