Design and test of driver and readout ASICs for scientific CCD detectors

In order to implement the driver and readout functions for a variety of scientific CCD detectors, especially for the prime-focus optical camera of the 2.5-meter Wide Field Survey Telescope (WFST), including decreasing the size of electronics and reducing the total power dissipation, two Application-specified Integrated Circuits (ASIC) were designed. One is used for CCD drivers and named as Bias-Clock-Driver ASIC (BCDA), which provides multi-channel clocks and bias voltages, the other is for CCD video signal processing and called CCD-Video-Readout ASIC (CVRA). The first prototype of BCDA and CVRA has been finished with the Global Foundries 180 nm BCDlite technology. In this paper, the design and layout of two ASICs, the design of testing system, the function and performance testing of two ASICs are introduced. The test results show that the high level range of clock is from 8 V to 16 V. The rise/fall time of parallel clock is several microseconds and the frequency is more than 100 kHz. The rise/fall time of serial clock is dozens of nanoseconds and the frequency is more than 1 MHz. The noise of the readout circuit is 9.2 e(-) when the readout speed is 100 kHz. The test results indicate that this design has achieved the goal of functional verification. And performance will be improved in subsequent design, especially in readout noise.