Comparison of Synchronous and Asynchronous FIR Filter Architectures

The Internet of Things requires developing ultralow power platforms embedding actuators, sensors, and signal processors. In order to limit the power consumption of such systems, nonuniform sampling schemes are very promising solutions, especially if coupled to event-driven circuitries. This strategy allows reducing the amount of sampled data, the system activity, and then the power consumption. Moreover, High-Level Synthesis (HLS) helps designers in rapidly developing ultra-low power platforms. In this article, we present a comparison of the uniform and non-uniform schemes in term of activity and power consumption. This evaluation is performed on Finite Impulse Response (FIR) filters in three different flavors: a synchronous filter using a classical sampling scheme and two asynchronous filters implementing a nonuniform sampling scheme, where one has been manually designed and the other generated by HLS. The filters have been designed in CMOS 350 nm and 40 nm. The filter manually designed provides an area reduction of 8 % and depending on the signal and the application, it is able to consume from 6.6 to 43 times less energy than the synchronous version. The filter produced by HLS exhibits an area reduction of 12%, and consume from 3.3 to 28 times less energy.