A Historical Perspective on Hardware AI Inference, Charge-Based Computational Circuits and an 8 bit Charge-Based Multiply-Add Core in 16 nm FinFET CMOS

The second wave of AI is about statistical learning of low dimensional structures from high dimensional data. Inference is done using multilayer, data transforming networks using fixed point arithmetic with parameters that have limited precision (4–16 bits). In this paper we give a historical perspective on hardware AI inference deep Artificial Neural Networks (ANNs) or in short Deep Neural Networks (DNN) and deep learning. We review custom chip implementations of ANNs from thirty years ago and from the more recent publications in the last five years. With only few exceptions, hardware AI architectures are digital but we argue that if done right, i.e. in the charge domain, analog computation will have a role in future hardware AI systems. We make our discussion concrete by presenting the architecture, implementation and measurements from a mixed-signal, charge-based 8-bit analog multiplier for limited precision linear algebra in AI systems. Using a capacitor array, and charge redistribution, the architecture performs the multiplication operation in the charge domain at the thermal noise limit with near minimum energy dissipation. The charge redistribution multiplier core was fabricated in a 16 nm FinFET CMOS process, with measured energy 1.4 fJ for the analog multiplication operation. Compared to a conventional digital implementation synthesized and simulated in the same technology, the proposed design achieves the same performance at 37% less energy.