Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard.

In order to support real-time HD video requirements for mobile and real time applications, energy-efficient design is the need of the hour for such low-cost devices. HEVC is the latest video compression standard that achieves high compression ratio and high bit-rate over existing architecture(H.264) but at the cost of higher computational complexity. HEVC incorporates integer DCT as an essential transform scheme for compressing the successive video frames. Approximate Integer DCT implementations with quality as a major constraint are proposed which consider the properties of transform matrices as prescribed by HEVC. A systematic approximation strategy has been introduced to achieve a reasonable quality-energy trade-off. The proposed 1-D architectures have reduced arithmetic complexity and less hardware resources when implemented on Artix-7 FPGA. A 56% reduction in resource utilization and 62% reduction in ASIC power when implemented on CMOS 180 nm technology is obtained compared with the reference DCT implementations and an improvement in coding performance is achieved as compared with the current work on approximated DCT architectures.