A Timing Pixel Front-End Design for HEP Experiments in 28 nm CMOS Technology

This work describes the design of a low-power low-jitter, analog front-end for timing-pixel radiations sensors. The circuit will provide the input stage for the front-end ASIC proposed for the TimeSpOT project that will be manufactured in a commercial 28 nm CMOS process. This front-end is designed to be part of 4D tracking detectors for future high data rate high energy physics experiments. This research aims at realizing 55 μm × 55 μm pixels with sub 100 ps resolution within less then 10 μW power consumption.