A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET

Armin Tajalli, M. Bastani,Dario Carnelli, C. Cao, J. Fox,Kiarash Gharibdoust, D. Gorret, A. Gupta, C. Hall, A. Hassanin,Klaas Hofstra,Brian Holden,Ali Hormati,John Keay,Yohann Mogentale, G. Paul, V. Perrin, J. Phillips, S. Raparthy,Amin Shokrollahi,David Stauffer, R. Simpson, A. Stewart,Giuseppe Surace,Omid Talebi Amiri, Anton Truffa, A. Tschank, R. Ulrich, C. Walter, A. Singh

2019 Symposium on VLSI Circuits（2019）

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摘要

A 1.02pJ/b USR link carrying 416.67 Gb/s/mm die edge (500Gb/s aggregated data rate) in 16nm FinFET, while occupying 2.4mm ² , is presented. To enable dense routing over conventional package material, a modified correlated NRZ signaling with low sensitivity to ISI, Xtalk, and common-mod noise has been developed. A matched CTLE/slicer topology has been employed to enhance robustness of the receiver over PVT. A very wideband Rx PLL tracks the majority of Tx jitter, resulting in significant power saving by relaxing Tx design constraints.

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关键词

Serial communication,USR link,chip-to-chip communication,PLL,clock forwarding,CTLE,slicer,MCM

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