Shielding Logic Locking from Redundancy Attacks

The security of logic locking has been extensively examined under the threat model that assumes the availability of an activated IC. Recently, structural attacks such as ones based on redundancy analysis have challenged the viability of logic locking even when stringent measures are taken to preclude access to an activated IC. In this paper, we propose a gate selection based logic locking technique to identify key gate insertion sites such that the redundancy level deviates minimally under all key assignments. The proposed logic locking technique is evaluated on a set of benchmark circuits to confirm its resistance against redundancy analysis based attacks.