A Short-Transfer Model for Tightly-Coupled CPU-FPGA Platforms

Due to the cost of repeated data movement between CPU and FPGA, the use of FPGA-based accelerators has traditionally been limited to offloading long-running tasks from the CPU to programmable logic. Although modern heterogeneous platforms, such as Zynq and HARP, reduce the costs of CPU-FPGA data transfers, the traditional offload model is cemented as the popular choice. For these systems to become truly heterogeneous, the utilisation of all computational resources should be optimised. In particular, the CPU and FPGA should cooperate by dividing the workload between them so as to maximize system throughput. We first derive a model that predicts the optimum partitioning of a workload between hardware and software. We then measure the performance of short transfers between CPU and FPGA on the Zynq CPU-FPGA platform. Such transfers are essential to efficiently synchronise between cooperating hardware and software tasks. Finally, we demonstrate how our derived model can be used to choose the optimum workload partitioning to within 8% of the optimum for an accumulator task and predict its execution time within 12%.