An Extrinsic Device and Leakage Mechanism in Advanced Bulk FinFET SRAM

A previously unrecognized vertical-extrinsic device in advanced 7-nm FinFET SRAM structures is identified and characterized for the first time. The ON-current for this vertical-extrinsic device is modulated by gate bias and exhibits a process-dependent threshold behavior. The ON-state of this parasitic device can exceed several nanoamperes and become the dominant mechanism in the static power of an SRAM array. Aggressively pushed ground rules used to achieve competitive SRAM density can result in exposure in FinFET-based SRAMs to this parasitic leakage path; n-Well and p-well dopant profiles, alignments, and dimensions must be carefully controlled to avoid this leakage mechanism in high-density FinFET SRAM arrays.