Cycling Induced Trap Generation and Recovery Near the Top Select Gate Transistor in 3D NAND

Cycling induced Vt shift of top select gate transistor (TSG) and the physical mechanism is studied in three dimensional (3D) NAND flash memory. It is found that the distribution of TSG Vt shifts higher during memory cells Program/Erase (P/E) cycling. The TSG Vt shift can recover after removal of cycling stress. A physical model of hot holes induced trap generation is proposed for above observations. It is considered that hot holes generated by high channel potential gradient during erase can break the =Si-H bonds at the poly-Si grain boundary and the poly-Si/SiO 2 , interface, causing TSG Vt tail shift and parallel shift, respectively. And the degradation can recover due to re-passivation of =Si-H bonds after stress removal. A TSG bias optimization scheme is demonstrated to reduce the hot holes generation and suppress the TSG abnormal Vt shift during cell P/E cycling.