6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS

Pen-Jui Peng,Jeng-Feng Li,Li-Yang Chen,Jri Lee

2017 IEEE International Solid-State Circuits Conference (ISSCC)（2017）

Cited 105|Views194

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Abstract

Ultra-high speed data links such as 400GbE continuously push transceivers to achieve better performance and lower power consumption. This paper presents a highly parallelized TRX at 56Gb/s with integrated serializer/deserializer, FFE/CTLE/DFE, CDR, and eye-monitoring circuits. It achieves BER<;10 ^-12 under 24dB loss at 14GHz while dissipating 602mW of power.

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Key words

PAM-4-NRZ transceiver,CMOS,ultra-high speed data links,eye-monitoring circuit,CDR,FFE-CTLE-DFE circuit,serializer-deserializer circuit,BER,bit rate 56 Gbit/s,size 40 nm,loss 24 dB,frequency 14 GHz,power 602 mW

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