Ge Cmos Gate Stack And Contact Development For Vertically Stacked Lateral Nanowire Fets
2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)(2018)
Abstract
We present (i) a novel, thermally stable Atomic Layer Deposition (ALD) high-k dielectric stack that, for the first time, has the potential to meet all gate stack requirements for both n- and p-channel Ge FETs, (ii) record low contact resistivity for n-Ge/metal contacts using an implant-free contact scheme with successful implementation into a single nanowire (NW) Ge nFET baseline, (iii) single NW Ge pFETs with short-channel effect (SCE) immunity down to 24 nm physical gate length, of which electrical data show excellent agreement with calibrated models and (iv) demonstration of Ge-channel vertically stacked lateral NW FETs using a 300 mm VLSI compatible platform.
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Key words
single nanowire Ge nFET,Atomic Layer Deposition high-k dielectric stack,p-channel Ge FET,contact resistivity,n-Ge/metal contacts,vertically stacked lateral nanowire,Ge-channel vertically stacked lateral NW FETs,short-channel effect immunity,single NW Ge pFETs,implant-free contact scheme,Ge
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