Tunability Of Parasitic Channel In Gate-All-Around Stacked Nanosheets
2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)(2018)
Abstract
For the first time, a comprehensive study going from the integration of 3D stacked nanosheets Gate-All-Around (GAA) MOSFET devices to SPICE modeling is proposed. Devices have been successfully fabricated on SOI substrates using a replacement high-kappa metal gate process and self-aligned-contacts. Back biasing is herein efficiently used to highlight a drastic improvement of electrostatics in the upper GAA Si channels. Advanced electrical characterization of these devices enabled us to calibrate a new version of physical compact model (LETI-NSP) in order to assess the performance of ring oscillators for different configurations of GAA FETs integrating up to 8 vertically stacked Si channels.
MoreTranslated text
Key words
Gate-All-Around stacked nanosheets,3D stacked nanosheets Gate-All-Around MOSFET devices,SPICE modeling,SOI substrates,self-aligned-contacts,advanced electrical characterization,physical compact model,parasitic channel tunability,high- κ metal gate process,GAA Si channels,vertically stacked Si channels,GAA FET,Si
AI Read Science
Must-Reading Tree
Example
![](https://originalfileserver.aminer.cn/sys/aminer/pubs/mrt_preview.jpeg)
Generate MRT to find the research sequence of this paper
Chat Paper
Summary is being generated by the instructions you defined