Recent Advance On Floating Random Walk Based Capacitance Solver For Vlsi Circuit Design
2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)（2018）
Abstract
Capacitance extraction for interconnect parasitics modeling is the basis of accurate circuit simulation and physical verification for quality integrated circuit (IC) design. Due to its scalability and reliability, the floating random walk (FRW) based solver has been widely used for the capacitance extraction. In this paper, the recently developed techniques on distributed parallel FRW solver and for handling complex floating metals are presented. With them, the efficiency and accuracy of capacitance extraction/simulation for very large-scale integration (VLSI) circuit design are remarkably improved.
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Key words
floating random walk based capacitance solver,capacitance extraction,very large-scale integration circuit design,FRW based solver,complex floating metals,distributed parallel FRW solver,floating random walk based solver,quality integrated circuit design,physical verification,accurate circuit simulation,interconnect parasitics modeling,VLSI circuit design
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