Phase-Locked Loop of SerDes for Satellite Laser Communication
2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT)（2018）
Abstract
Based on TSMC 55G process, a phase-locked loop (PLL) design is presented, which is used in the SerDes system of satellite laser communication equipment. The codec in the satellite laser communication equipment needs SerDes system to provide the fractional-N frequency-division clock signal. The transmission rate of the SerDes system is 5Gb/s. The clock frequency range of fractional-N PLL is 2.5GHz-20/7GHz. The power consumption is 27mW at 1.8V.
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Key words
satellite laser communication equipment,SerDes system,fractional-N frequency-division clock signal,TSMC 55G process,phase-locked loop design,codec,voltage 1.8 V,power 27.0 mW,bit rate 5 Gbit/s
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