Technique for Asymmetric Source/Drain Resistance Extraction on a Single Gate Length MOSFET
2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)(2018)
摘要
A simple inline measurement technique for extracting the individual resistance components of the source, drain, and channel on a single MOSFET device using DC measurements is proposed. Modeling data is used to prove the efficacy of the technique. This method can be applied to symmetric or asymmetric devices.
更多查看译文
关键词
parasitic resistance,device characterization
AI 理解论文
溯源树
样例
![](https://originalfileserver.aminer.cn/sys/aminer/pubs/mrt_preview.jpeg)
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要