Variable Gain Distributed Amplifier with Capacitive Division

In this work the design of variable gain amplifiers using the distributed amplifier topology with capacitive division is explored. The effects of the capacitive division technique on gain, line attenuation and bandwidth of the amplifier in different bias states are analyzed by means of circuit simulations and theoretical investigations. The designed 3-stage circuit shows a gain range from -0.1 to 11.9 dB at a bandwidth of at least 1.2 - 83 GHz over all measured gain states. At maximum gain the upper 3 dB frequency exceeds 110 GHz. The circuit fabricated in a 130nm SiGe BiCMOS technology has a chip area of 0.4mm(2) and a power consumption of 72mW at the maximum gain state.