Power Noise Sensitivity of Micro-Processors with Adaptive Clocking
2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)(2018)
Abstract
Adaptive clocking becomes more popular and it is very effective to mitigate low and middle frequency power noise impact on timing or fmax of micro-processor designs. In the meantime, clock-data jitter tracking can effectively address high frequency noises. This paper is to consider these two effects and examine power noise sensitivity in the full bandwidth of noises.
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Key words
adaptive clocking,jitter,noise sensitivity,power supply noises
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