Package design challenges and optimizations in density efficient (Intel® Xeon® processor D) SoC

Qi Zhu,Srikrishnan Venkataraman,Chunfei Ye,Arun Chandrasekhar

2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)（2016）

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摘要

Xeon®-D[1] brings the high performance of Xeon® processors into a dense, low-power System-on-Chip (SoC). This paper addresses the importance of cost-performance trade off optimization for the Xeon®-D package. It describes how to determine the low cost package factors (size, footprint, pin map and layer count) without compromising the performance of the system. 10GbE signal integrity design and HSD pin map optimization are discussed. Low power architecture and package power delivery features including FIVR are presented in the paper as well.

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关键词

package design,density efficient SoC,Intel Xeon Processor D,low-power system-on-chip,cost-performance trade off optimization,Xeon-D package,low cost package factors,signal integrity design,HSD pin map optimization,low-power architecture,package power delivery,FIVR

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