Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal–oxide–semiconductor devices*

The effect of nitric oxide (NO) annealing on charge traps in the oxide insulator and transition layer in n-type 4H-SiC metal-oxide-semiconductor (MOS) devices has been investigated using the time-dependent bias stress (TDBS), capacitance-voltage (C-V), and secondary ion mass spectroscopy (SIMS). It is revealed that two main categories of charge traps, near interface oxide traps (N-niot) and oxide traps (N-ot), have different responses to the TDBS and C-V characteristics in NO-annealed and Ar-annealed samples. The N-niot are mainly responsible for the hysteresis occurring in the bidirectional C-V characteristics, which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor. However, N-ot is mainly responsible for the TDBS induced C-V shifts. Electrons tunneling into the N-ot are hardly released quickly when suffering TDBS, resulting in the problem of the threshold voltage stability. Compared with the Ar-annealed sample, N-niot can be significantly suppressed by the NO annealing, but there is little improvement of N-ot. SIMS results demonstrate that the N-niot are distributed within the transition layer, which correlated with the existence of the excess silicon. During the NO annealing process, the excess Si atoms incorporate into nitrogen in the transition layer, allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of N-niot.