Slow response in gate current–voltage characteristics of metal–oxide–semiconductor structures on the 4H-SiC face

We have investigated the gate current-voltage (I-g-V-g) characteristics of n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and p-MOS capacitors on the 4H-SiC(000 (1) over bar) face. The gate current response to a change in gate voltage has a very slow part, which has been considered to be due to slow traps in the oxide near the SiO2-SiC interface. However, we found that the slow response can be explained by fast interface traps if the traps have a relatively large concentration. Carrier injection into the interface traps results in a change in the surface potential, and this suppresses the further injection of carriers. This new model can explain many electrical properties such as the constant-current behavior in the Ig-Vg characteristics, which was confirmed by one-dimensional (1D) device simulation. According to this model, the interface traps will not be occupied up to the surface Fermi level within the general time scale of the measurement. In spite of the arguments described above, slow traps also probably exist near the interface between SiO2 and SiC. (C) 2016 The Japan Society of Applied Physics