Erratum to “Efficient VLSI Implementation of Scaling of Signed Integer in RNS { }” [Oct 13 1936-1940]

Thian Fatt Tay,Chip-Hong Chang,Jeremy Yung Shern Low

IEEE Transactions on Very Large Scale Integration (VLSI) Systems（2016）

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摘要

The authors would like to point out the following correction in the total power consumptions recorded in Table IV of the published article [1]. The total power consumptions of the proposed design and the design [2] in comparison should be corrected as shown in Table I.

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关键词

Very large scale integration,Power demand,Clocks,Simulation,Delays,Digital signal processing chips,Logic circuits

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