Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean Constraints.

ISPD(2019)

Cited 15|Views413
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Abstract
In this paper, we propose a routing flow for nets within a standard cell that generates layout of standard cells without any design rule violations. Design rules, density rules for metal fill, and pin-access requirements are modeled via Boolean formulas for discrete layout objects on grids. Formulas are translated into a single Boolean satisfiability problem (SAT). Having constraints on net connectivity and candidate routes, the SAT solver produces legal and complete routing concurrently for all nets satisfying mandatory pin-access and density requirements. A SAT-based optimization engine minimizes undesired layout patterns such as DFM (design-for-manufacturing) hot spots.
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Key words
Standard cell libraries, routing, DFM, layout, FinFET, SAT, Boolean satisfiability, metal fill
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