PDN design and sensitivity analysis using synthesized models in DDR SI/PI co-simulations

A common method for analyzing a PCB Power Distribution Network (PDN) involves performing model extractions on a CAD layout, checking the impedance vs frequency plot, and using the model in transient simulations. The proposed method uses a synthesized RLC model as a replacement for CAD layout and that it closely mimics a realistic CAD layout extracted model. Such a synthesized model is easily created using self and transfer impedance equations (that can either be created manually or be incorporated into an algorithm for automatic generation). The RLC synthesized models are passive and causal and have been shown to eliminate common problems in transient simulations. The models can be created quickly and easily with varying PDN impedances and effective topologies and have been shown to correlate very well with models extracted from CAD layouts in both the frequency and time domains. Such models can potentially replace extracted PCB models and enable efficient design space exploration to determine PCB PDN targets. The technique can also be applied to PKG PDN models.