Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $\mu$ A Sensing Resolution, and 17.5-nS Read Access Time

A new MRAM reference and sensing circuit that can achieve <±1 $\mu \text{A}$ resolution and 17.5 nS read access from −40 °C to 125 °C is presented in this paper. A trimmable current-mode latch-type sense amplifier (CLSA) with hybrid-resistance-reference (HRR) and cell location compensation is proposed to resolve small read margin of MRAM. Silicon data measurement is presented to demonstrate a logic-process compatible, fully functional 16-Mb perpendicular MRAM in 40-nm CMOS process. Similar read circuit design concept can be applied to other technology nodes. Another test chip designed in 22 nm achieves wafer level average raw bit-error-rate (BER) of ~0.2 ppm and less than 2-ppm BER for 95th percentile chip.