Device Design of Vertical Nanowire III-V Heterojunction TFETs for Performance Enhancement

In this paper, we analyze the heterojunction GaAs0.4Sb0.6/In0.65Ga0.35As TFET with vertical nanowire structure and non-uniform diameter design (V-NW TFET with non-uniform diameter). A thin channel layer (T-i) is inserted between the gate and source regions for improving the on currents, and the non-uniform diameter thickness is used for suppressing the leakage current (I-min). The bandgap widening induced by quantum confinement is considered in this work. The leakage current can be suppressed by using thinner diameter thickness of the drain/channel junction (T-DC), and the gate-to-drain underlap design is used to further reduce the ambipolar leakage. The impacts of T-i, T-DC, source and drain doping concentrations, and gate-to-source overlap length (L-ovs) on the V-NW TFET have been investigated. Compared with the ultra-thin body (UTB) TFET, the proposed V-NW TFET with non-uniform diameter (thin T-DC ) exhibits 2 times larger I-on (236 mu A/mu m) due to the increased line tunneling area, and 59.8 times lower leakage current (5.5x10(-10) mu A/mu m).