Transmission Line Pulse Test Method for Estimating SEB Performance of $n$ -Channel Lateral DMOS Power Transistors

A novel wafer-level method is described for predicting lateral-diffused MOS transistor single-event burnout (SEB) levels to assist device engineers in the development phase of radiation-hardened power transistors. The method uses a transmission-line pulse (TLP) tester together with scribeline transistor test structures. Technology computer-aided design (TCAD) is used to estimate static Id-Vdss beh...