A 40nm Split Gate Embedded Flash Macro with Flexible 2-in-1 Architecture, Code Memory with 140mhz Read Speed and Data Memory with 1M Cycles Endurance
2017 SYMPOSIUM ON VLSI CIRCUITS（2017）
Key words
embedded flash macro,eflash macro,code storage,enhanced read margin,temperature adaptive reference scheme,flexible array partitioned scheme,junction temperature,data storage memory,size 40 nm,frequency 140 MHz,temperature 160 C
AI Read Science
Must-Reading Tree
Example
Generate MRT to find the research sequence of this paper
Chat Paper
Summary is being generated by the instructions you defined