Influence of stress induced CT local layout effect (LLE) on 14nm FinFET

Pei Zhao,Shesh Mani Pandey,Edmund Kenneth Banghart,Xiaoli He,Ram Asra, Vinayak Mahajan,Haojun Zhang,Baofu Zhu, Kenta Yamada,Linjun Cao,Pala Balasubramaniam,Manoj Joshi,Manfred Eller,Francis Benistant,Srikanth Samavedam

2017 Symposium on VLSI Technology（2017）

Cited 15|Views214

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Abstract

In this paper, we present a new local layout effect in 14nm FinFET due to different CT layout designs (CT extension, CT spacing, and PC past RX distance). Based on 14nm FinFET experimental data, the CT LLE effect induces up to 50mV Vtsat shift, and ~20% current change. NFET performance is enhanced by ~7%, while the PFET performance shows slight degradation. Based on TCAD simulation, the CT LLE is fully analyzed and explained by the tensile stress induced in the inter-layer dielectric (ILD).

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Key words

stress induced CT local layout effect,LLE,FinFET,CT layout designs,CT extension,CT spacing,PC past RX distance,NFET performance,PFET performance,TCAD simulation,tensile stress,inter-layer dielectric,size 14 nm

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